The present invention relates generally to a delay circuit and more particularly to a delay circuit incorporating a reset-based static delay in its forward delay line.
Delay circuits are used where it is necessary to have two signals which have a known relationship to one another. For example, phase locked loop circuits (PLL) are designed to minimize the phase difference between two signals. The PLL passes an input or reference signal into a delay line. Typically, the amount of delay in a PLL's forward delay line is adjusted until the PLL's output signal has the same phase desired phase as the input or reference signal. When the phase difference of the two signals approaches zero (or is within a specified tolerance), the phase of the two signals is said to be “locked”.
Another example of delay circuits are delay locked loop circuits (DLL). A DLL is similar to a PLL, but instead of producing an output signal that has the same phase as an input signal or reference signal, the DLL passes the input or reference signal into a delay line. Typically, the amount of delay in a DLL's forward delay line is adjusted until the DLL's output achieves a desired predefined phase delay relative to the input or reference signal. The DLL is referred to as “locked” when the output achieves the desired predefined phase delay.
Delay circuits (e.g., PLL, DLL, etc.) may include both a static delay portion and a variable delay portion. Static delay generally refers to delay element(s) which have a fixed amount delay and which, once inserted, predominantly remain within the route of a signal of interest (i.e., an input or reference signal, such as a clock signal). Variable delay refers to delay element(s) which have an adjustable amount of delay and/or to delay element(s) which are regularly switched into and out of (i.e., bypassed by) the route of the signal of interest. The total amount of delay that the delay circuit is capable of providing is a combination of both the static delay portion and the variable delay portion (e.g., the amount of delay in the DLL's forward delay line).
The variable delay portion, for example, may be implemented using either analog components or digital components. The components are used to create delay stages which may be linked together to form a delay chain. Due to the way each delay stage is adjusted, analog delay chains have continuous delay adjustments whereas digital delay chains have discreet step adjustments. More specifically, the delay of each stage within an analog delay chain is varied by controlling the analog bias voltages (for example, from a phase detector) supplied to each stage. In contrast, the amount of delay in the digital delay chain is varied by switching one or more delay stages into or out of the delay chain.
One problem with prior art delay circuits occurs when there is not enough delay within the forward variable delay line to lock the output signal to the input or reference signal. For example, a digital DLL may not have enough delay stages in the delay chain to lock the output to an input signal that has a clock frequency outside of the DLL's locking range. Typically, when the DLL reaches the end of the delay chain (i.e., all of the delay stages in the delay chain have been activated), it will reset itself and attempt to lock again. For clock frequencies outside of the locking range, the DLL continuously resets because it can never find a lock.
In applications where the DLL may not have enough delay to lock securely, extra delay stages may be added to the delay chain during the DLL's design, the delay of each stage within the delay chain may be increased, and/or permanent static delay may be added into the DLL's forward delay line.
The addition of extra delay stages to the delay chain, however, adversely effects the layout size of the circuit. For example, a full delay stage may require additional space for a shift register to set the entry point and in some cases an opposing measure control delay line must also be supplied for proper initialization.
Increasing the delay of each stage within the delay chain may adversely effect the delay line resolution. For example, each stage may include one or more transistors whose delay may be increased by extending the transistor(s) channel length. However, a transistor with a longer channel typically has a coarser delay increment which results in the decrease in resolution.
Permanently inserting static delay into the forward path may work for some frequencies (i.e., will allow the DLL to lock because the lock point is actually reduced by the additional static delay), however, permanently adding static delay into the forward path only shifts the DLL's profile and does not prevent the DLL from failing to lock at other frequencies. Furthermore, the static delay is a function of process, voltage, and temperature variations, thus a DLL with additional permanent static delay is more susceptible to jitter.
Thus, a need exists for a delay circuit that has a large locking range, tight locking characteristics, and good tracking over PVT variations, and which overcomes the other limitations inherent in prior art.